Multi-level metal (MLM) systems are comprised of alternating levels or layers of metal and dielectric. Each level of metal in a conventional MLM system typically includes an aluminum-copper or aluminum-copper-silicon layer overlying a barrier metal layer such as titanium nitride or titanium tungsten. Portions of a level of metal that are adjacent to, overlie, or underlie a via are typically at least twice as wide as other portions of the level of metal that are not near the via. The extra width in the level of metal ensures that portions of the underlying substrate or that lower portions of the MLM system are not inadvertently electrically shorted due to the misalignment of a via in the dielectric layer and over-etching. However, the extra width in the level of metal increases the minimum line width and pitch of the teasel of metal and can increase memory cell and device sizes. Consequently, the MLM system requires more surface area and increases the footprint of the semiconductor die.
Accordingly, a need exists for a semiconductor component that has a multi-level interconnect system that does not require larger line widths near vias, that is compatible with existing semiconductor manufacturing processes, that is cost effective, and that does not significantly increase the cycle time for manufacturing a semiconductor component.